ICs have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing functionality. The semiconductor processing technologies that produce these ICs have advanced to the point where complete systems, including memories, can be reduced to a single IC or application-specific IC (ASIC). ASICs are usually made up of standard functional units, called “hard marcrocells” or sometimes “IP blocks,” and buses and logic (so-called “glue logic”) that tie the hard-macrocells together. It is a common practice for the manufacturers of such ICs to thoroughly test device functionality at the manufacturing site. Because of the increasing complexity of new designs, test development costs now account for a large percentage of the total ASIC development cost.
Before ICs (sometimes called “chips”) are released for shipment by a manufacturer, they typically undergo a variety of testing procedures. This testing is necessary because perfect yields are difficult to achieve. It is not uncommon for a certain percentage of unpackaged ASICs to contain hard macrocells that fail testing processes, due largely to non-systemic manufacturing defects and degradation faults. Such manufacturing issues are likely to increase as process geometries continue to shrink and the density of memory cells increases.
A number of ASIC testing strategies have evolved, many of which involve use of an external tester, or Automated Test Equipment (ATE). If the ASIC is accessible from input/output (I/O) pins, either directly or by multiplexing, a hardware test mode can be employed. In this mode, a production test system gains access to the ASIC directly by transmitting signals to, and receiving signals from, the ASIC. While this strategy does not require any chip area other than some simple multiplexing circuitry, it is limited to on-chip memories and other circuitry accessible via I/O pins. Another drawback of this approach is that ATE capabilities are generally not available to end users once the devices have been shipped, making difficult the task of detecting faults occurring after shipment.
If an embedded memory is buried deeply within an ASIC, built-in self-test (BIST) is often considered the most practical and efficient test methodology and is becoming increasing popular with semiconductor vendors. BIST allows the ASIC to be tested quickly with a reasonably high degree of fault coverage, without requiring complex external test equipment and large amounts of external access circuitry. One advantage BIST has over many traditional testing methods is that with BIST, memory or logic circuitry can be tested at any time in the field. This capability offers some degree of continued fault protection.
BIST refers in general to any test technique in which test vectors are generated internal to an IC or ASIC. Test vectors are sequences of signals that are applied to an IC to determine if it is performing as designed. BIST can be used to test circuitry located anywhere on the ASIC without requiring dedicated I/O pins, and can be used to test memory or logic circuitry every time power is applied to the ASIC, thereby allowing an ASIC to be easily tested after it has been incorporated in an end product. A number of software tools exist for automatically generating BIST circuitry, including RAMBIST Builder by LSI Logic of Milpitas, Calif. Such software produces area-efficient BIST circuitry for testing memories, and reduces time-to-market and test development costs.
In the BIST approach, a test pattern generator and test response analyzer are incorporated directly into the device to be tested in the form of a dedicated, hard-wired circuit. BIST operation is controlled by supplying an external clock and employing a simple commencement protocol. BIST test results are typically compressed—usually to the level of “passed” or “failed.” At the end of a typical structured BIST test, or “run,” a simple pass/fail signal is asserted, indicating whether the device passed or failed the test. Intermediate pass/fail signals may also be provided, allowing individual circuits or groups of circuits to be analyzed. Unlike external testing approaches, at-speed testing with BIST is readily achieved. BIST also alleviates the need for long and convoluted test vectors and may function as a surrogate for functional testing or scan testing. Further, since the BIST structures are hard-wired and remain active on the device, BIST can be employed at the board or system level to yield reduced system testing costs, and to reduce field diagnosis and repair costs.
In addition to the aforementioned testing procedures, manufacturers employ a number of techniques to repair faulty ASICs when feasible. Such techniques include bypassing defective cells using laser procedures and fused links that cause address redirection or data corruption. However, such techniques are limited to one-time repair and require significant capital investment. Further, these techniques may leave ICs useless if the repaired ASICs become defective after shipment from the manufacturing site (perhaps due to electromigration or other burn-in related defects)—even where test equipment is available to end users, traditional field repairs have been expensive, time consuming and largely impracticable.
In order to enhance the repair process, on-chip built-in self repair (BISR) circuitry for repairing faulty memory cells has evolved. BISR circuitry functions internal to the IC without detailed interaction with external test or repair equipment. In the BISR approach, suitable test algorithms are preferably developed and implemented in BIST or BIST-like circuitry. Following execution of the test patterns, the BISR circuitry analyzes the BIST “signature” (results) and, in the event of detected faults, automatically reconfigures the defective memory utilizing redundant memory elements to replace the defective ones. An ASIC incorporating BISR is therefore defect-tolerant. The assignee of the present invention, LSI Logic Corporation, has addressed different methods of repairing faulty memory locations employing BIST and BISR circuitry, as disclosed in U.S. patent application Ser. No. 08/970,030, entitled “Method for Separating Prime and Repaired Integrated Circuits Incorporating Built-in Self Test and Built-in Self Repair Circuitry,” which is hereby incorporated by reference as if set forth in its entirety.
BISR compliments BIST because it takes advantage of on-chip processing capabilities to enable only functioning hard macrocells and glue logic, rather than using an expensive and slow laser burning process to try to fix the faulty ones.
During the testing process, it is often desirable to separate so-called “prime die” (IC die in which no redundant BISR memory components were utilized during initial testing) from “repaired die.” Separating IC die in this manner provides an indication of quality and fault tolerance. Because the BIST and BISR circuitry of an IC continue to be functional in the field, any BISR redundancy resources not expended during initial testing are available to repair faults that may occur in the field. As a consequence, prime die have a higher degree of fault tolerance, and can often be sold by manufacturers for a premium.
Unfortunately, as stated above, both conventional BIST and BISR circuitry takes the form of hard-wired logic, which invariably occupies chip area that could otherwise be employed by circuitry useful in the normal operation of the ASIC. Further, if the BIST or BISR circuitry itself is manufactured with a fault, its operation may be significantly altered, potentially compromising or prohibiting any test or repair function it would be tasked with performing.
Accordingly, what is needed in the art is a better way to incorporate BIST or BISR capabilities into an ASIC. More specifically, what is needed is an improved BIST or BISR for VLSI or WSI circuitry.